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Extra resources for Advanced Xilinx Fpga Design With Ise
All Rights Reserved Timing Report Structure • Timing Constraints – – • Data Sheet Report – • Setup, hold, and clock-to-out times for each I/O pin Timing Summary – • Number of paths covered and number of paths that failed for each constraint Detailed descriptions of the longest paths Number of errors, Timing Score Timing Analyzer Settings – Allows you to easily duplicate the report Timing Closure with Timing Analyzer - 10 © 2003 Xilinx, Inc. All Rights Reserved Report Example • Constraint summary – – – • Detailed path description – – • Number of paths covered Number of timing errors Length of critical path Delay types are described in the data sheet Worst-case conditions assumed, unless pro-rated Total delay – – OFFSET paths have two parts Logic/routing breakdown Timing Closure with Timing Analyzer - 11 © 2003 Xilinx, Inc.
8% route) net_2 has a long delay, even though fanout is low Location column reveals that bad placement is the cause – Go to Edit → Preferences in the Timing Analyzer to show this column Timing Closure with Timing Analyzer - 16 © 2003 Xilinx, Inc. All Rights Reserved Poor Placement: Solutions • Timing-driven Map, if the placement is caused by packing unrelated logic together – – • PAR extra effort or MPPR options – • Cross-probe to the Floorplanner to see what has been packed together Timing-driven Map is covered in the Advanced Implementation Options module Covered in the Advanced Implementation Options module Floorplanning or RLOC constraints, if you have the skill – Covered in the Advanced FPGA Implementation course Timing Closure with Timing Analyzer - 17 © 2003 Xilinx, Inc.
All Rights Reserved Objectives After completing this lab, you will be able to: • • • Create a core using the Xilinx CORE Generator™ system Instantiate a core into an HDL design Perform behavioral simulation on a design that contains a core CORE Generator System - 9 - 32 © 2003 Xilinx, Inc. All Rights Reserved Lab Design: Correlate and Accumulate CORE Generator System - 9 - 33 © 2003 Xilinx, Inc. All Rights Reserved Channel FIFO Block CORE Generator System - 9 - 34 © 2003 Xilinx, Inc. All Rights Reserved Lab Overview • • • Generate a dual-port block RAM core Replace an instantiated library primitive with the core Perform behavioral simulation on the design – Testbench file provided CORE Generator System - 9 - 35 © 2003 Xilinx, Inc.